A prior art analog to digital converter 1 with offset correction is shown in FIG. 1. In particular, in FIG. 1 a capacitive pseudo-differential SAR (Successive Approximation Register) analog to digital converter 1 is shown, comprising a capacitive digital to analog converter C-DAC, a comparator CMP, a logic circuit SAR-LOG adapted to execute a SAR algorithm, a timing circuit TIM-SEQ adapted to provide control signals to the different components of the analog to digital converter 1 upon receipt of a signal CONVERSION REQUEST adapted to request the converter 1 to perform a new analog to digital conversion, and offset register OFF-REG adapted to store a measured or estimated digital value which is representative of the offset voltage value at the summing nodes NS+, NS−. In the example shown in FIG. 1 the summing nodes Ns+, NS− represents common nodes to which respectively first ends of a first array and a second array of switched capacitors (not shown in the figures) are connected. Such analog to digital converter is for example disclosed in the paper “A 2.7 mW 1MSps 10b Analog-to-Digital Converter with Built in Reference Buffer and 1LSB Accuracy Programmable Input Ranges”, Confalonieri P., Zamprogno M., Girardi F., Nicollini G., Nagari A., Solid-State Circuits Conference, 2004, ESSCIRC 2004, September 2004, pp. 255-258.
A known method to cancel the offset of the analog to digital converter 1 consists in measuring it with a dedicated routine at the power-up or during testing phase, storing it as a digital value in the offset register OFF-REG and analogically subtracting the stored value from the analog input voltage VIN to be converted. EP 1887702 B1 discloses a switched capacitance analog to digital converter in which an estimated or measured offset can be analogically added or subtracted to an analog input signal to be converted.
FIG. 2 shows a set TIM1 of the most relevant timing logic signals that can be used during the analog to digital conversion and offset correction in the prior art analog to digital converter shown in FIG. 1. When a conversion request is issued (i.e. when the signal CONVERSIONREQUEST goes at high level), the array of switched capacitors connected to the summing node NS+ is charged between VIN and VCM, while the other array of switched capacitors connected to the summing node NS− is charged between GND and VCM, through VINCHARGE and VINSAMPLE high level signals. VCM represents the input common mode voltage of the comparator CMP. The signal VINSAMPLE through the MOS switches M1 and M2 is adapted to selectively force the summing nodes NS+ and NS− to the input common mode voltage VCM. When the charging transient is over, the signal VINSAMPLE is reset by the timing sequencer TIM-SEQ, freezing the voltage to be converted. With a slight delay the timing sequencer TIM-SEQ:                by means of the signal VINCHARGE turns off the switches of the arrays of switched capacitors that were connected to the input analog signal VIN; and        by means of the high level on the signal SARENABLE enables the SAR algorithm to search for the output digital code which represents the best possible digital approximation of the input analog signal VIN. As indicated in the time diagram TIM 1 of FIG. 2, when the signal SARBUS goes at high level a first time period MSB TENT is allocated for performing the first comparison useful for resolving during the subsequent time period MSB-1 the most significant bit (MSB) of the output digital code, and the subsequent time periods MSB-1 TENT, . . . , LSB TENT are allocated for performing the subsequent comparisons and resolving the subsequent bits down to the least significant bit (LSB) of the digital output code (OUT-COD). Meanwhile, through the digital to analog converter C-DAC, a digital to analog conversion of the content of the offset register OFF-REG is done, so to cancel the offset effects from the system. As anticipated, said content is an offset digital value representing an estimation or measure of the voltage offset at said first common node NS+, NS−. Such offset can have many contributions: the offset of the comparator CMP, the mismatch between the switches M1 and M2, and an offset that could appear on different ground nodes, because of bonding inductances or resistive paths, as a result of digital switching activity just before the falling front of the signal VINSAMPLE.        
The existing solutions for the offset correction are affected by several problems. In particular, if the offset correction code is stored in an OTP (One Time Programmable) memory during testing phase, this is done at a given temperature; this means that a temperature variation, as well as device degradation, gives rise to an error in offset correction, introducing an error that can be considered unacceptable. Otherwise, if the offset correction code is stored at every power-up phase (which is often not possible), device degradation would be properly corrected, as well as the temperature drift. But as soon as the temperature changes during the power-up time, before the next power-down, once again these would lead to an offset cancellation error.
The most important contribution to this offset drift is usually coming from to the comparator CMP, but also from the changes in the charge injection for switches M1 and M2 (due to their threshold voltage variations, as well as variations in electron mobility, or in the fall time of the digital signal that turn them off), or changes in the offset coming from different ground paths (due to the variations of the currents that are flowing through them just before the falling front of the signal VINSAMPLE).
Historically, a possible approach to reduce such offset drift is to connect during the analog input VIN sampling phase the differential outputs of the comparator CMP to the summing nodes NS+ and NS—, in order to cancel at each conversion (except for a little error due to the finite gain of the comparator) the comparator offset. This reduces the problem but it's not enough, and moreover, can imply longer sampling periods, if there is the need to guarantee an appropriate settling time with a small comparator CMP that has a restrained current consumption.